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Introduction One of the important offerings of the RISC-V Instruction Set Architecture (ISA) is the ability to customize and extend the base instruction set. An initial reaction to...
Introduction My previous blog talked about the importance of instruction set standardization for ecosystem stability and growth through the use of profiles. And standardization is...
Actual RVA23 hardware and useful performance – for a certain price
Since May we have been benchmarking the SpacemiT K3 RISC-V SoC as one of the first to market RISC-V chips supporting the RVA23 profile. The SpacemiT K3 has shown how far RISC-V per...
One of the RISC-V SoCs we have been most looking forward to this year is the SpacemiT K3 that features the X100 RISC-V cores that are RVA23 compliant and among the first readily av...
HFI proposes a familiar PC-style route from power-on to operating system
Recently I published some initial SpacemiT K3 benchmarks for that first-to-market RISC-V RVA23 SoC with the K3 Pico-ITX mini computer. In there was a comparison against modern Inte...
Along with the many x86/x86_64 improvements and some ARM64 architecture improvements (albeit slowed down by the AI/LLM noise affecting the development pace), the RISC-V architectur...
A homebrew PC and mini-mainframe were only the warm-up for Yuri Zaporozhets' latest operating system
StarFive has announced a new partnership with server CPU design company LECARC to develop a new generation of RISC-V server processors designed for intelligent edge computing. The...
Beijing’s sovereign stack ambitions strengthen
An important one-liner is set to come for Linux 7.2 to enable ESWIN SoC support by default for RISC-V kernel builds. This change will allow default RISC-V kernel builds in turn to...
The next version will have 32,000 MCUs
A post merge-window change that landed in Linux Git overnight ahead of tomorrow's Linux 7.2-rc2 release is bumping the default limit on the number of supported CPU cores for RISC-V...
Vortex 3.0 RISC-V GPGPU, Pragtical SDL GPU Backend, NVIDIA RTX Spark Launch Today's Highlights Today's top stories highlight significant advancements in open-source GP...
The Harmonic Firmware Initiative "HFI" is trying to provide a generic, standardized power-on firmware experience for RISC-V boards. Akin to the x86 world with having immediate grap...
Similar to Linux 7.2 enabling Eswin SoC support by default in the RISC-V "defconfig" kernel build, UltraRISC RISC-V coverage is also now being enabled by default for RISC-V kernel...
Last year, we noted three upcoming high-performance RISC-V SoCs to watch out for: Zhihe A210, SpacemiT K3, and UltraRISC UR-DP1000. The K3 has already been launched, and I’ll work...
Motor driver IC specialist Fortior Technology has recently introduced the FU75xx dual-core motor control MCU family, pairing a 32-bit RISC-V core and the company’s proprietary 2nd-...
The open-source developers at Georgia Tech working on Vortex as an OpenCL-compatible RISC-V GPGPU implementation are out with their next major release for this open-source GPU desi...
QSOE 0.1 has made its debut as a QNX-inspired, dual kernel architecture open-source operating system just targeting RISC-V...
The newest GCC 17 compiler code has landed support for -mcpu=spacemit-x100 and -mtune=spacemit-x100 targeting for the SpacemiT X100 RISC-V core...
Aheesa Digital Innovations has achieved a significant milestone in India’s semiconductor journey with the tape-out of VIHAAN-I, the country’s first domestically designed RISC-V-bas...
Potential takeover would represent significant commitment to the open instruction set architecture
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