Social Media Ideas for Monolithic 3D Integration

Monolithic 3D Integration Breakthrough Could Reshape the Semiconductor Roadmap

University of Illinois researchers led by Professor Cao Qing demonstrate a monolithic 3D integration technique that stacks transistor layers at low temperatures with near-perfect y...

University of Illinois Team Advances Monolithic 3D Chip Design

Insider Brief PRESS RELEASE — Researchers led by Illinois Grainger Engineering professor Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performan...

Monolithic 3D Integration Enables Self-Powered Smart Electronics

In a groundbreaking advance poised to redefine the future of self-sustaining electronics, researchers have unveiled a monolithic three-dimensional integrated circuit that seamlessl...

Stacking semiconductor chips like skyscrapers to enhance performance

A team of researchers from POSTECH (Pohang University of Science and Technology) in South Korea has unveiled a groundbreaking technique for stacking more than ten ultrathin semicon...

Chinese AI Chip Makers Turn to 3D Stacking for a 'Curve-Overtaking' Advantage

With EUV lithography tools restricted, Chinese AI chip designers are betting on 3D hybrid bonding and stacking technology to bypass traditional scaling limits and compete on perfor...

Samsung First To Build 3D Stacked Transistors

Samsung’s unveiling of the first 3D stacked transistor marks a new era in semiconductor design, as stacking could theoretically double device density instantly compared to current...

Prototype Software Improves 3D Chip Optimization

A chip design tool treats multilayer chips as one 3D structure, reducing wire length by 30% while improving performance and thermal management. Peking University’s School of Integr...

Chinese AI Chip Makers Turn to 3D Stacking to Break Through Process Bottlenecks

Chinese AI chip companies are increasingly turning to 3D stacking technology as a strategic alternative to advanced process node upgrades, as the industry confr...

The Next Computing Revolution May Come From Stacking Chips Like Skyscrapers

Researchers may have unlocked the future of computing by turning flat silicon chips into densely stacked 3D architectures. For decades, the semiconductor industry has boosted compu...

Ion-beam origami unlocks wafer-scale 3D photonic systems

Broad-beam ion etching folds flat nanostructures into 3D photonic devices across a 4-inch wafer while preserving speed, uniformity, and optical function.

В США испытали метод стекового производства 3D-чипов, кратно превосходящий по плотности все современные

Следование закону Мура едва не прекратилось из-за физических пределов производства полупроводников, но учёные уже спешат ухватить годами выполнявшийся принцип за ускользающий хвост...

Revolutionizing Chip Design: Sequential Silicon Stacking to Push Moore’s Law Further

For over fifty years, the relentless pursuit to enhance computing power has centered on shrinking transistors and densely packing them onto silicon chips. This well-established tra...

2D Chip Opens New Path for Computing

A computer built with a 2D semiconductor integrates more than 1,400 transistors on one chip, demonstrating a path toward AI and edge computing. Researchers from Nanjing University,...

AMD Unveils Adaptive SoC With 32 GB of Memory-on-Package Embedded DRAM

Announced today, the new AMD Versal Premium Gen 2 MoP SoCs boost performance by integrating memory on-package. It cuts board space by 60% while gaining 288 GB/s bandwidth and 15-ye...

Инженеры уложили HBM на бок — память стала быстрее, холоднее и вместительнее

Инженеры предложили новый способ наращивания памяти для ускорителей ИИ и графических процессоров: вместо укладки кристаллов DRAM привычной «башней», как в HBM, их предлагается уста...

AMD Versal Premium Gen 2 MoP adaptive SoC integrates 32GB LPDDR5X to shrink board footprint by 60%

AMD has announced the Versal Premium Gen 2 Memory-on-Package (MoP) adaptive SoCs, adding an integrated memory option to the Premium Gen 2 family, a topic we covered back in Novembe...

Jusung Engineering commercializes ALG transistor integration technology

Jusung Engineering announced Monday that it has shipped what it described as the world’s first atomic layer growth (ALG) transistor full-integration semiconductor manufacturing equ...

Ferroelectric memory Chip Advances Generative AI Hardware

The technology integrates two key generative AI functions into a single ferroelectric memory platform for improved power efficiency. Researchers at  Seoul National University have...

Japan's Kioxia to take on Samsung with wafer-bonding tech in memory race

Exclusive CEO Interview: Rebellions’ NPU Leverages Memory-Centric Chiplets

The Korean unicorn packages four NPU dies with 144 GB of HBM3E and bets on an open software stack to serve large language models at lower cost per token.

Single-crystal diamond interposer improves the performance of high-power electronics

By using a thin layer of diamond to manage excessive heat, researchers can boost the speed and energy-efficiency of next-generation wireless devices.

Photonic Integration Moves Chip Towards Petabit-Speed

New optical couplers could simplify photonic chip integration while enabling faster, more energy-efficient data transmission. Researchers at the Massachusetts Institute of Technolo...

Chip Cooling Technique for AI

A new in-package cooling innovation tackles rising heat challenges in 3D-stacked memory chips, improving thermal efficiency and stability for AI workloads while enabling higher ban...

MIT Chip Builds Real-Time 3D Maps for Robots on the Power of One LED

Called Gleanmer, the 16-nm system-on-chip swaps memory-hungry voxels for compact Gaussian “blobs” to map and navigate at roughly 6 mW.