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A chip design tool treats multilayer chips as one 3D structure, reducing wire length by 30% while improving performance and thermal management. Peking University’s School of Integr...
Beyond fabs, this startup is tackling a hidden semiconductor challenge that could redefine chip design and expand opportunities for innovation. India’s semiconductor ambitions are...
Building AI and 3D chips is getting harder. New design, test, and IP tools aim to reduce complexity and speed development. Synopsys has expanded its portfolio of AI-powered chip de...
Insider Brief PRESS RELEASE — Researchers led by Illinois Grainger Engineering professor Qing Cao have demonstrated a scalable way to directly and sequentially stack high-performan...
Can AI help engineers design chips faster? A new set of tools can create RTL code, check designs, estimate power and performance, and reduce development time. Rapidus Corporation h...
Synopsys announces Multiphysics Fusion products and early customers to lower prevent respins and lower costs
With EUV lithography tools restricted, Chinese AI chip designers are betting on 3D hybrid bonding and stacking technology to bypass traditional scaling limits and compete on perfor...
New agentic EDA capability is positioned to execute design and verification tasks with minimal human intervention, aiming to compress simulation-heavy workflows and speed time-to-s...
Enables engineers to capture design decisions, simulations, and optimisation workflows on an executable whiteboard, helping teams preserve expertise, automate processes, and prepar...
Samsung’s unveiling of the first 3D stacked transistor marks a new era in semiconductor design, as stacking could theoretically double device density instantly compared to current...
As AI systems push data speeds higher, engineers are facing a simulation problem — and a new tool aims to solve it in one workflow. Keysight Technologies has added an Electrical-Op...
University of Illinois researchers led by Professor Cao Qing demonstrate a monolithic 3D integration technique that stacks transistor layers at low temperatures with near-perfect y...
Can 2D semiconductors replace silicon? A new pilot line targets 5nm-equivalent chips without relying on EUV lithography by 2029. Shanghai-based semiconductor start-up Yuanjiwei has...
A computer built with a 2D semiconductor integrates more than 1,400 transistors on one chip, demonstrating a path toward AI and edge computing. Researchers from Nanjing University,...
One-two punch offers a glimpse of how low-precision AI can complement high-precision simulations
Chinese AI chip companies are increasingly turning to 3D stacking technology as a strategic alternative to advanced process node upgrades, as the industry confr...
A new browser-based simulation platform is helping engineers accelerate loss and thermal analysis in power electronics design, reducing development time from hours to minutes throu...
For over fifty years, the relentless pursuit to enhance computing power has centered on shrinking transistors and densely packing them onto silicon chips. This well-established tra...
Broad-beam ion etching folds flat nanostructures into 3D photonic devices across a 4-inch wafer while preserving speed, uniformity, and optical function.
Следование закону Мура едва не прекратилось из-за физических пределов производства полупроводников, но учёные уже спешат ухватить годами выполнявшийся принцип за ускользающий хвост...
Researchers may have unlocked the future of computing by turning flat silicon chips into densely stacked 3D architectures. For decades, the semiconductor industry has boosted compu...
A team of researchers from POSTECH (Pohang University of Science and Technology) in South Korea has unveiled a groundbreaking technique for stacking more than ten ultrathin semicon...
What happens when transistor dimensions approach atomic limits? New chipmaking technologies are helping improve AI chip performance and efficiency. Applied Materials has introduced...
A new in-package cooling innovation tackles rising heat challenges in 3D-stacked memory chips, improving thermal efficiency and stability for AI workloads while enabling higher ban...
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